The QD62D is Mitsubishi Electric’s 2-channel high-speed counter module for the MELSEC-Q programmable controller series with built-in SSI (Synchronous Serial Interface) absolute encoder input capability — providing direct absolute position reading from SSI-protocol absolute encoders at power-up without requiring a home return cycle, combined with standard incremental pulse counting at up to 500 kpps for applications where both absolute position initialisation and high-speed incremental counting are required from a single intelligent function module. As the SSI-capable variant in the QD62 counter module family, the QD62D eliminates the need for separate SSI interface modules and incremental counter modules in absolute positioning systems. In stock at Atlantech Drives. Request your quote within 24-48 hours with worldwide shipping and 12-month warranty.
What Is the QD62D?
The QD62D is a MELSEC-Q series intelligent function module providing two independent channels of high-speed pulse counting and SSI absolute encoder reading. Each channel can be configured in GX Works2 to operate as either a standard incremental pulse counter (AB quadrature, CW/CCW, or single-phase, up to 500 kpps) or as an SSI absolute encoder interface (reading the encoder’s absolute position word at power-up and on demand). In SSI mode, the QD62D generates the SSI clock signal and reads the encoder’s serial absolute position data, converting it to a 32-bit integer stored in the buffer memory for the CPU to access via FROM instructions or auto-refresh. This power-up absolute position reading eliminates the home return cycle that incremental encoder systems require, enabling machines to determine their exact mechanical position immediately after power restoration — critical for vertical axis applications, heavy load positioners, and any system where driving to a home sensor position before production can resume would cause unacceptable restart delays or safety hazards. The module also provides a coincidence output on each channel (inherited from the QD62E architecture) for hardware-speed threshold detection at sub-0.1 ms response time.
Key Technical Specifications
- Model: QD62D
- Counter Channels: 2
- Incremental Input: AB quadrature (×1, ×2, ×4), CW/CCW, single-phase — up to 500 kpps
- SSI Absolute Encoder Input: Supported — clock frequency configurable (100 kHz to 500 kHz)
- SSI Data Length: 13 to 25 bits (configurable)
- SSI Encoding: Gray code or binary (configurable)
- Counter Range: -2,147,483,648 to +2,147,483,647 (32-bit signed)
- Coincidence Output: 1 per channel (transistor, 24 VDC, less than 0.1 ms response)
- Latch Input: External latch per channel
- Current Consumption (5 VDC internal bus): 0.42 A
- External Power Supply: 24 VDC ±10%, 0.15 A (required)
- Operating Temperature: 0°C to 55°C
- Weight: Approx. 0.22 kg
Series Comparison & Selection Guide
The QD62 counter module family for MELSEC-Q includes three variants addressing different application requirements. The standard QD62 provides 2-channel 500 kpps incremental counting without coincidence output — appropriate for simple position monitoring and speed measurement where hardware coincidence detection is not required. The QD62E adds coincidence output to the QD62 specification, providing sub-0.1 ms hardware threshold detection for cut-to-length, print registration, and cam switching applications using incremental encoders. The QD62D builds on the QD62E specification by adding SSI absolute encoder input, making it the correct choice for any application where the encoder provides SSI absolute position data — most commonly with hollow-shaft or through-shaft rotary absolute encoders on turntables, rotary indexers, and vertical axis lifts, and with linear absolute encoders on linear actuators and CMM measuring machines. When selecting between the QD62E and QD62D, the determining factor is the encoder type: if the application uses incremental encoders only, specify the QD62E; if any encoder provides SSI absolute data, specify the QD62D. The QD62D’s SSI interface supports the BiSS (Bidirectional Serial Synchronous) protocol subset used by many modern absolute encoders, in addition to standard SSI — verify the encoder’s protocol specification before selection.
Expert Tips
When commissioning the QD62D with an SSI absolute encoder, the most common configuration error is an incorrect SSI data length or Gray code/binary encoding selection — these parameters must match the encoder’s output specification exactly, as an incorrect setting causes the module to decode the serial bit stream incorrectly and report erroneous absolute position values. Obtain the encoder’s SSI specification from the encoder manufacturer’s datasheet rather than from the machine documentation, as machine documentation may contain errors transcribed from the original commissioning notes. Verify the decoded position value at a known mechanical reference point (such as a mechanical hard stop or a reference mark on the machine) by reading the QD62D’s absolute position register via GX Works2’s buffer memory monitor at that position — confirm the decoded value matches the expected encoder count for that position before proceeding with machine calibration. For SSI encoder cable runs longer than 10 m, use shielded twisted-pair cable with a minimum of 4 twisted pairs (one pair per signal: Clock+/Clock-, Data+/Data-, plus shield and power) — the SSI clock and data lines are differential signals and must be routed as matched-impedance twisted pairs to maintain signal integrity at SSI clock frequencies above 200 kHz. At power-up, allow at least 500 ms for the SSI encoder to complete its internal initialisation before issuing the first SSI read command from the QD62D — some multi-turn absolute encoders require additional time to read their non-volatile turn counter and complete the power-up self-check before they are ready to respond to SSI clock inputs.
Frequently Asked Questions
Q: Can the QD62D read a Heidenhain EnDat absolute encoder, or only SSI encoders?
A: The QD62D supports SSI protocol encoders only — it does not support Heidenhain EnDat 2.1 or EnDat 2.2, which use a different bidirectional command/response protocol than the unidirectional SSI clock/data format. For EnDat encoder integration with MELSEC-Q, a separate EnDat-to-SSI converter module or an EnDat-to-analogue/pulse converter must be used to convert the EnDat signal to a format the QD62D can accept. Many Heidenhain encoders with EnDat interface also provide a parallel incremental TTL output — using the incremental output with the QD62D’s standard counter input mode is an alternative approach for applications not requiring power-up absolute position without homing.
Q: Can both channels of the QD62D operate as SSI absolute encoder inputs simultaneously?
A: Yes. Both channels can be independently configured as SSI absolute encoder inputs in GX Works2’s buffer memory parameter settings, enabling simultaneous absolute position reading from two independent SSI encoders. Each channel has its own independently configurable SSI clock frequency, data length, and encoding format, allowing the two channels to interface with different encoder types or resolutions from the same module.
Q: What is the power-up absolute position reading time for the QD62D?
A: After module power-up, the QD62D initiates the SSI read cycle automatically and completes the absolute position reading within approximately 2 ms for a 25-bit SSI encoder at 500 kHz clock frequency. The absolute position value is available in the buffer memory for the CPU to read within the first CPU scan cycle after the module completes initialisation, which typically occurs within 500 ms of power-up. The buffer memory status register indicates when the absolute position reading is valid and ready for use by the CPU program.
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